View MC74AC161_104502.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC74AC161 MC74ACT161 MC74AC163 MC74ACT163 Synchronous Presettable Binary Counter
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74AC163/ 74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. * * * * * Synchronous Counting and Loading High-Speed Synchronous Expansion Typical Count Rate of 125 MHz Outputs Source/Sink 24 mA ACT161 and ACT163 Have TTL Compatible Inputs
VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 D SUFFIX CASE 751B-05 PLASTIC N SUFFIX CASE 648-08 PLASTIC
SYNCHRONOUS PRESETTABLE BINARY COUNTER
LOGIC SYMBOL
1 *R 2 CP 3 P0 4 P1 5 P2 6 P3 7 CEP 8 GND PE P0 P1 P2 P3 CEP CET TC CP *R Q0 Q1 Q2 Q3
PIN NAMES CEP CET CP MR SR P0-P3 PE Q 0 -Q 3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (161) Asynchronous Master Reset Input (163) Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output
*MR for 161 *SR for 163
FACT DATA 5-1
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
FUNCTIONAL DESCRIPTION
The MC74AC161/74ACT161 and MC74AC163/74ACT163 count modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the 161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (161), synchronous reset (163), parallel load, count-up and hold. Five control inputs -- Master Reset (MR, 161), Synchronous Reset (SR, 163), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR MODE SELECT TABLE
*SR L H H H H PE X L H H H CET X X H L X CEP X X H X L Action on the Rising Clock Edge ( ) Reset (Clear) Load (Pn Qn) Count (Increment) No Change (Hold) No Change (Hold)
0 15 14 13 12 11 10 9
(161) or SR (163) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The MC74AC161/74ACT161 and MC74AC163/74ACT163 use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the MC74AC568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations: Count Enable = CEP*CET*PE TC = Q0*Q1*Q2*Q3*CET
STATE DIAGRAM
1 2 3 4 5 6 7 8
*For 163 only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
LOGIC DIAGRAM
P0 PE 161 CEP CET 163 ONLY 163 P1 P2 P3
TC
CP
CP
161 ONLY D CD Q0
CP
CP Q
D Q Q0 DETAIL A DETAIL A DETAIL A DETAIL A
MR 161 SR 163 Q0 Q1 Q2 Q3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FACT DATA 5-2
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
MAXIMUM RATINGS*
Symbol VCC Vin Vout Iin Iout ICC Tstg Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC VCC or GND Current per Output Pin Storage Temperature Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 Unit V V V mA mA mA C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout Supply Voltage DC Input Voltage, Output Voltage (Ref. to GND) VCC @ 3.0 V tr, tf Input Rise and Fall Time (Note 1) AC Devices except Schmitt Inputs VCC @ 4.5 V VCC @ 5.5 V tr, tf TJ TA IOH IOL Input Rise and Fall Time (Note 2) ACT Devices except Schmitt Inputs Junction Temperature (PDIP) Operating Ambient Temperature Range Output Current -- High Output Current -- Low -40 25 VCC @ 4.5 V VCC @ 5.5 V Parameter AC ACT Min 2.0 4.5 0 150 40 25 10 ns/V 8.0 140 85 -24 24 C C mA mA ns/V Typ 5.0 5.0 Max 6.0 5.5 VCC V Unit V
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
FACT DATA 5-3
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
DC CHARACTERISTICS
74AC Symbol Parameter VCC (V) TA = +25C Typ VIH Minimum High Level Input Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOLD IOHD ICC Maximum Input Leakage Current Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 8.0 0.002 0.001 0.001 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 74AC TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 75 -75 80 V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A V *VIN = VIL or VIH -12 mA IOH -24 mA -24 mA IOUT = 50 A V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA VI = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
VIL
Maximum Low Level Input Voltage
V
VOH
Minimum High Level Output Voltage
V
V
A mA mA A
* All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
FACT DATA 5-4
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC CHARACTERISTICS (For Figures and Waveforms -- See Section 3)
74AC161 Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Maximum Count Frequency Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay CET to TC Propagation Delay MR to Qn Propagation Delay MR to TC 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 70 110 2.0 1.5 1.5 1.5 3.0 2.0 3.5 2.0 2.0 1.5 2.5 2.0 2.0 1.5 3.5 2.5 TA = +25C CL = 50 pF Typ 111 167 7.0 5.0 7.0 5.0 9.0 6.0 8.5 6.5 5.5 3.5 6.5 5.0 6.0 5.5 10.0 8.5 12.0 9.0 12.0 9.5 15.0 10.5 14.0 11.0 9.5 6.5 11.0 8.5 12.0 9.5 15.0 13.0 Max 74AC161 TA = -40C to +85C CL = 50 pF Min 60 95 1.5 1.0 1.5 1.5 2.5 1.5 2.5 2.0 1.5 1.0 2.0 1.5 1.5 1.5 3.0 2.5 13.5 9.5 13.0 10.0 16.5 11.5 15.5 11.5 11.0 7.5 12.5 9.5 13.5 10.0 17.5 13.5 Max MHz ns ns ns ns ns ns ns ns 3-3 3-6 3-6 3-6 3-6 3-6 3-6 3-6 3-6 Unit Fig. No.
* Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms -- See Section 3)
74AC163 Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPLH tPHL tPLH tPHL Maximum Count Frequency Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay CET to TC 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 70 110 2.0 1.5 1.5 1.5 3.0 2.0 3.5 2.0 2.0 1.5 2.5 2.0 TA = +25C CL = 50 pF Typ 95 140 7.5 5.5 8.5 6.0 9.5 7.0 11.0 8.0 7.5 5.5 8.5 6.0 12.5 9.0 12.0 9.5 15.0 10.5 14.0 11.0 9.5 6.5 11.0 8.5 Max 74AC163 TA = -40C to +85C CL = 50 pF Min 60 95 1.5 1.0 1.5 1.5 2.5 1.5 2.5 2.0 1.5 1.0 2.0 1.5 13.5 9.5 13.0 10.0 16.5 11.5 15.5 11.5 11.0 7.5 12.5 9.5 Max MHz ns ns ns ns ns ns 3-3 3-6 3-6 3-6 3-6 3-6 3-6 Unit Fig. No.
* Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
FACT DATA 5-5
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC OPERATING REQUIREMENTS
74AC161 Symbol Parameter VCC* (V) Typ ts th ts th ts th tw tw tw trec Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW MR Pulse Width, LOW Recovery TIme MR to CP 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 6.0 3.5 -7.0 -4.0 6.5 4.0 -6.0 -3.5 3.0 2.0 -3.5 -2.0 2.0 2.0 2.0 2.0 3.0 2.5 -2.0 -1.0 TA = +25C CL = 50 pF 74AC161 TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 13.5 8.5 -1.0 0 11.5 7.5 0 0.5 6.0 4.5 0 0 3.5 2.5 4.0 3.0 5.5 4.5 -0.5 0 16.0 10.5 -0.5 0 14.0 8.5 0 1.0 7.0 5.0 0 0.5 4.0 3.0 4.5 3.5 7.5 6.0 0 0.5 ns ns ns ns ns ns ns ns ns ns 3-9 3-9 3-9 3-9 3-9 3-9 3-6 3-6 3-6 3-9
* Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
FACT DATA 5-6
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC OPERATING REQUIREMENTS
74AC163 Symbol Parameter VCC* (V) Typ ts th ts th ts th ts th tw tw Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5.5 4.0 -7.0 -5.0 5.5 4.0 -7.5 -5.5 5.5 4.0 -7.5 -5.0 3.5 2.5 -4.5 -3.0 3.0 2.0 3.0 2.0 TA = +25C CL = 50 pF 74AC163 TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 13.5 8.5 -1.0 0 14 9.5 -1.0 -0.5 11.5 7.5 -1.0 -0.5 6.0 4.5 0 0 3.5 2.5 4.0 3.0 16.0 10.5 -0.5 0 16.5 11.0 -0.5 0 14.0 8.5 -0.5 0 7.0 5.0 0 0.5 4.0 3.0 4.5 3.5 ns ns ns ns ns ns ns ns ns ns 3-9 3-9 3-9 3-9 3-9 3-9 3-9 3-9 3-6 3-6
* Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
FACT DATA 5-7
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
DC CHARACTERISTICS
74ACT Symbol Parameter VCC (V) TA = +25C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Additional Max. ICC/Input Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 8.0 0.6 0.001 0.001 1.5 1.5 1.5 1.5 4.49 5.49 74ACT TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 80 V V V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A *VIN = VIL or VIH -24 mA IOH -24 mA IOUT = 50 A *VIN = VIL or VIH 24 mA IOL 24 mA VI = VCC, GND VI = VCC - 2.1 V VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
V
V
V
A mA mA mA A
* All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
FACT DATA 5-8
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC CHARACTERISTICS (For Figures and Waveforms -- See Section 3)
74ACT161 Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Maximum Count Frequency Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP or Qn (PE Input HIGH or LOW) Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay CET to TC Propagation Delay MR to Qn Propagation Delay MR to TC 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 115 1.5 1.5 2.0 1.5 1.5 1.5 1.5 2.5 TA = +25C CL = 50 pF Typ 125 8.0 8.0 11.0 11.0 7.5 8.0 8.0 10.0 9.5 10.5 11.0 12.5 8.5 9.5 10.0 13.5 Max 74ACT161 TA = -40C to +85C CL = 50 pF Min 100 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.0 10.5 11.5 12.5 13.5 10.0 10.5 11.0 14.5 Max MHz ns ns ns ns ns ns ns ns 3-3 3-6 3-6 3-6 3-6 3-6 3-6 3-6 3-6 Unit Fig. No.
* Voltage Range 5.0 V is 5.0 V 0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms -- See Section 3)
74ACT163 Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPLH tPHL tPLH tPHL Maximum Count Frequency Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to Qn (PE Input HIGH or LOW) Propagation Delay CP to TC Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay CET to TC 5.0 5.0 5.0 5.0 5.0 5.0 5.0 120 1.5 1.5 2.5 3.0 2.0 2.0 TA = +25C CL = 50 pF Typ 140 5.5 6.0 7.0 8.0 5.5 6.0 10.0 11.0 11.5 13.5 9.0 10.0 Max 74ACT163 TA = -40C to +85C CL = 50 pF Min 105 1.5 1.5 2.0 2.0 1.5 2.0 11.0 12.0 13.5 15.0 10.5 11.0 Max MHz ns ns ns ns ns ns 3-3 3-6 3-6 3-6 3-6 3-6 3-6 Unit Fig. No.
* Voltage Range 5.0 V is 5.0 V 0.5 V.
FACT DATA 5-9
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC OPERATING REQUIREMENTS
74ACT161 Symbol Parameter VCC* (V) Typ ts th ts th ts th tw tw tw trec Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW MR Pulse Width, LOW Recovery Time MR to CP 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 7.0 -3.0 6.0 -3.5 4.0 -2.0 2.0 2.0 3.0 0 TA = +25C CL = 50 pF 74ACT161 TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 9.5 0 8.5 - 0.5 5.5 0 3.0 3.0 3.0 0 11.5 0 9.5 - 0.5 6.5 0 3.5 3.5 7.5 0.5 ns ns ns ns ns ns ns ns ns ns 3-9 3-9 3-9 3-9 3-9 3-9 3-6 3-6 3-6 3-9
* Voltage Range 5.0 V is 5.0 V 0.5 V.
FACT DATA 5-10
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC OPERATING REQUIREMENTS
74ACT163 Symbol Parameter VCC* (V) Typ ts th ts th ts th ts th tw tw Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width HIGH or LOW Clock Pulse Width (Count) HIGH or LOW 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 4.0 -5.0 4.0 -5.5 4.0 -5.5 2.5 -3.0 2.0 2.0 TA = +25C CL = 50 pF 74ACT163 TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 10.0 0.5 10.0 -0.5 8.5 -0.5 5.5 0 3.5 3.5 12.0 0.5 11.5 -0.5 10.5 0 6.5 0.5 3.5 3.5 ns ns ns ns ns ns ns ns ns ns 3-9 3-9 3-9 3-9 3-9 3-9 3-9 3-9 3-6 3-6
* Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 45 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V
FACT DATA 5-11
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
OUTLINE DIMENSIONS
N SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
9
-A-
16
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
9
16
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
FACT DATA 5-12
*MC74AC161/D*
MC74AC161/D

▲Up To Search▲

Price & Availability of MC74AC161

	To Download MC74AC161 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .